TSM4ND50 500v n - channel power mosfet 1 / 8 version: b08 to - 252 general description the tsm4 nd50 n - channel enhancement mode power mosfet is produced by planar stripe dmos technology. this advanced technology has been especially tailored to minimize on - state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for high efficiency switch mode power supply, power factor correction, electronic lamp ballast based on half bridge. featu res low gate charge typical @ 1 2 nc low crss typical @ 10 pf fast switching 100% avalanche tested improved dv/dt capability esd protection ordering information part no. package packing TSM4ND50cp ro to - 252 2,500pcs / 13 reel block diagram n - channel mosfet absolute maximum rating ( ta= 25 o c unless otherwise noted ) parameter symbol limit unit drain - source voltage v ds 5 00 v gate - source voltage v gs 30 v continuous drain current i d 3 a pulsed drain current i dm 1 2 a conti nuous source current (diode conduction) i s 3 a peak diode recovery (note 2) dv/dt 4.5 v/ns single pulse drain to source avalanche energy (note 3) e as 120 mj total power dissipation @ t c =25 o c p d tot 45 w operating junction and storage temperature ran ge t j , t stg - 55 to +150 o c thermal performance parameter symbol limit unit thermal resistance - junction to case r? jc 2.78 o c/w thermal resistance - junction to ambient r? ja 100 o c/w note s : surface mounted on fr4 board t 10sec product summary v ds (v) r ds(on) () i d (a) 500 2.7 @ v gs =10v 1.5 pin definition : 1. gate 2. drain 3. source
TSM4ND50 500v n - channel power mosfet 2 / 8 version: b08 electrical specifications ( ta = 25 o c unless otherwise noted ) parameter conditions symbol min typ max u nit static drain - source breakd own voltage v gs = 0 v, i d = 250ua bv dss 500 -- -- v drain - source on - state resistance v gs = 10v, i d = 1.5 a r ds(on) -- 2.3 2.7 gate threshold voltage v ds = v gs , i d = 250ua v gs(th) 3 .0 -- 4.5 v zero gate voltage drain current v ds = 5 00v, v gs = 0v i dss -- -- 1 ua gate body leakage v gs = 2 0v, v ds = 0v i gss -- -- 10 u a forward transconductance v ds = 15 v, i d = 1.5 a g fs -- 1.5 -- s dynamic b total gate charge q g -- 12 -- gate - source charge q gs -- 3.4 -- gate - drain charge v ds = 400v, i d = 3 a, v gs = 10v q gd -- 6.4 -- nc input capacitance c iss -- 310 -- output capacitance c oss -- 49 -- reverse transfer capacitance v ds = 25v, v gs = 0v, f = 1.0mhz c rss -- 10 -- pf switching c turn - on delay time t d(on) -- 22 -- turn - on rise time t r -- 9 -- turn - off delay time t d(off) -- 9 -- turn - off fall time v gs = 10v, i d = 1.5a, v dd = 25 0 v, r g = 4.7 t f -- 4.5 -- ns source drain diode source drain current i sd -- -- 3 a diode forward voltage i s = 3 a, v gs = 0v v sd -- -- 1. 6 v reverse recove ry time t f r -- 315 -- ns reverse recovery charge q f r -- 940 -- uc reverse recovery current v dd = 4 0v, i s = 3 a , di/dt = 100a/us, t j =150 c (see test circuit) i rrm -- 7.2 -- a notes: 1. p ulse test: pulse width 300us, duty cycle 2% 2. i sd <4.5a, di/dt<200a/us , vdd |